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cy62127dv30 mobl ? 1-mbit (64 k 16) static ram cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document number: 38-05229 rev. *m revised january 8, 2013 zebracy62127dv30 mobl ? 1-mbit (64 k 16) static ram features temperature ranges ? industrial: ?40 c to 85 c very high speed: 55 ns wide voltage range: 2.2 v to 3.6 v pin compatible with cy62127bv ultra-low active power ? typical active current: 0.85 ma at f = 1 mhz ? typical active current: 5 ma at f = f max ultra-low standby power easy memory expansion with ce and oe features automatic power-down when deselected available in pb-free 48-ball fbga and 44-pin tsop type ii packages functional description the cy62127dv30 is a high-performance cmos static ram organized as 64 k words by 16-bits. this device features advanced circuit design to provide ultra-low active current. this is ideal for providing more battery life? ? (mobl ? ) in portable applications such as cellular telephones. the device also has an automatic power-down feature that significantly reduces power consumption by 90% when addresses are not toggling. the device can be put into standby mode reducing power consumption by more than 99% when deselected (ce high or both bhe and ble are high). the input/output pins (i/o 0 through i/o 15 ) are placed in a high-impedance state when: deselected (ce high), outputs are disabled (oe high), both byte high enable and byte low enable are disabled (bhe , ble high) or during a write operation (ce low and we low). writing to the device is accomplished by taking chip enable (ce ) and write enable (we ) inputs low. if byte low enable (ble ) is low, then data from i/o pins (i/o 0 through i/o 7 ), is written into the location specified on the address pins (a 0 through a 15 ). if byte high enable (bhe ) is low, then data from i/o pins (i/o 8 through i/o 15 ) is written into the location specified on the address pins (a 0 through a 15 ). reading from the device is accomplished by taking chip enable (ce ) and output enable (oe ) low while forcing the write enable (we ) high. if byte low enable (ble ) is low, then data from the memory location specified by the address pins appear on i/o 0 to i/o 7 . if byte high enable (bhe ) is low, then data from memory appear on i/o 8 to i/o 15 . see the truth table at the back of this datasheet for a complete description of read and write modes. . 64k x 16 ram array i/o 0 ?i/o 7 row decoder a 8 a 7 a 6 a 5 a 2 column decoder a 11 a 12 a 13 a 14 a 15 2048 x 512 sense amps data in drivers oe a 4 a 3 i/o 8 ?i/o 15 ce we ble bhe a 0 a 1 a 9 power -down circuit bhe ble ce a 10 10 logic block diagram
cy62127dv30 document number: 38-05229 rev. *m page 2 of 14 contents product portfolio .............................................................. 3 pin configurations ........................................................... 3 maximum ratings ............................................................. 4 operating range ............................................................... 4 dc electrical characteristics .......................................... 4 capacitance ...................................................................... 4 thermal resistance .......................................................... 5 ac test loads and waveforms ....................................... 5 data retention characteristics ....................................... 5 switching characteristics ................................................ 6 truth table ....................................................................... 9 ordering information ...................................................... 10 ordering code definitions ..... .................................... 10 package diagrams .......................................................... 11 acronyms ........................................................................ 12 document conventions ................................................. 12 units of measure ....................................................... 12 document history page ................................................. 13 sales, solutions, and legal information ...................... 14 worldwide sales and design s upport ......... .............. 14 products .................................................................... 14 psoc solutions ......................................................... 14
cy62127dv30 document number: 38-05229 rev. *m page 3 of 14 product portfolio pin configurations . product v cc range (v) speed (ns) power dissipation operating, i cc (ma) standby i sb2 ( ? a) f = 1 mhz f = f max min typ max typ [1] max typ [1] max range typ [1] max cy62127dv30ll 2.2 3.0 3.6 55 0.85 1.5 5 10 industrial 1.5 4 we 1 2 3 4 5 6 7 8 9 10 11 14 31 32 36 35 34 33 37 40 39 38 top view tsop ii (forward) [2, 3] 12 13 41 44 43 42 16 15 29 30 v cc a 15 a 14 a 13 a 12 nc a 4 a 3 oe v ss a 5 i/o 15 a 2 ce i/o 2 i/o 0 i/o 1 bhe nc a 1 a 0 18 17 20 19 i/o 3 27 28 25 26 22 21 23 24 dnu v ss i/o 6 i/o 4 i/o 5 i/o 7 a 6 a 7 ble v cc i/o 14 i/o 13 i/o 12 i/o 11 i/o 10 i/o 9 i/o 8 a 8 a 9 a 10 a 11 we a 11 a 10 a 6 a 0 a 3 ce i/o 10 i/o 8 i/o 9 a 4 a 5 i/o 11 i/o 13 i/o 12 i/o 14 i/o 15 v ss a 9 a 8 oe v ss a 7 i/o 0 bhe nc a 2 a 1 ble v cc i/o 2 i/o 1 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 a 15 a 14 a 13 a 12 nc nc nc 3 2 6 5 4 1 d e b a c f g h fbga (top view) [2, 3] nc dnu v cc nc notes 1. typical values are included for reference only and are no t guaranteed or tested. typical values are measured at v cc = v cc(typ) , t a = 25 c. 2. nc pins are not connected to the die. expansion pins on fbga package: e4 - 2m, d3 - 4m, h1 - 8m, g2 - 16m, h6 - 32m 3. pin #23 of tsop-ii and e3 ball of fbga are dnu, which have to be left floating or tied to vss to ensure proper application.
cy62127dv30 document number: 38-05229 rev. *m page 4 of 14 maximum ratings exceeding maximum ratings may s horten the useful life of the device. user guidelines are not tested. storage temperature... ............... ............... ?65 c to +150 c ambient temperature with power applied ............. ............... ............... ?55 c to +125 c supply voltage to ground potential ................. ? 0.3 v to 3.9 v dc voltage applied to outputs in high z state [4] .................................. ? 0.3 v to v cc + 0.3 v dc input voltage [4] ............................... ? 0.3 v to v cc + 0.3 v output current into outputs (low) .............................. 20 ma static discharge voltage.......................................... > 2001 v (per mil-std-883, method 3015) latch-up current ..................................................... > 200 ma operating range range ambient temperature (t a ) v cc [5] industrial ?40 c to +85 c 2.2 v to 3.6 v dc electrical characteristics over the operating range parameter description test conditions ?55 unit min typ [6] max v oh output high voltage 2.2 ? v cc ? 2.7 i oh = ? 0.1 ma 2.0 ? ? v 2.7 ? v cc ? 3.6 i oh = ? 1.0 ma 2.4 ? ? v ol output low voltage 2.2 ? v cc ? 2.7 i ol = 0.1 ma ? ? 0.4 v 2.7 ? v cc ? 3.6 i ol = 2.1 ma ? ? 0.4 v ih input high voltage 2.2 ? v cc ? 2.7 1.8 ? v cc + 0.3 v 2.7 ? v cc ? 3.6 2.2 ? v cc + 0.3 v il input low voltage 2.2 ? v cc ? 2.7 ? 0.3 ? 0.6 v 2.7 ? v cc ? 3.6 ? 0.3 ? 0.8 i ix input leakage current gnd ? v i ? v cc ? 1 ? +1 a i oz output leakage current gnd ? v o ? v cc , output disabled ? 1 ? +1 a i cc v cc operating supply current f = f max = 1/t rc v cc = 3.6 v, i out = 0 ma, cmos level ? 5 10 ma f = 1 mhz ? 0.85 1.5 i sb1 automatic ce power-down current? cmos inputs ce ? v cc ? 0.2 v, v in ? v cc ? 0.2 v, v in ? 0.2 v, f = f max (address and data only), f = 0 (oe , we , bhe and ble ) ? 1.5 4 a i sb2 automatic ce power-down current? cmos inputs ce ? v cc ? 0.2 v, v in ? v cc ? 0.2 v or v in ? 0.2 v, f = 0, v cc = 3.6 v ? 1.5 4 a capacitance parameter [7] description test conditions max unit c in input capacitance t a = 25 c, f = 1 mhz v cc = v cc(typ) 8 pf c out output capacitance 8 pf notes 4. v il(min) = ?2.0 v for pulse durations less than 20 ns., v ih(max) = v cc + 0.75 v for pulse durations less than 20 ns. 5. full device operation requires linear ramp of v cc from 0 v to v cc(min) and v cc must be stable at v cc(min) for 500 ? s. 6. typical values are included for reference only and are not guaranteed or tested. typical values are measured at v cc = v cc(typ) , t a = 25 c. 7. tested initially and after any design or proc ess changes that may affect these parameters.
cy62127dv30 document number: 38-05229 rev. *m page 5 of 14 data retention waveform [11] thermal resistance parameter [8] description test conditions fbga tsop-ii unit ? ja thermal resistance (junction to ambient) still air, soldered on a 3 4.5 inch, two-layer printed circuit board 55 76 c/w ? jc thermal resistance (j unction to case) 12 11 c/w ac test loads and waveforms parameters 2.5 v (2.2 v ? 2.7 v) 3.0 v (2.7 v ? 3.6 v) unit r1 16600 1103 ? r2 15400 1554 ? r th 8000 645 ? v th 1.20 1.75 v data retention characteristics parameter description conditions min typ [9] max unit v dr v cc for data retention 1.5 ? ? v i ccdr data retention current v cc = 1.5 v, ce ? v cc ? 0.2 v, v in ? v cc ? 0.2 v or v in ? 0.2 v ? 3 ? a t cdr chip deselect to data retention time 0 ? ? ns t r [10] operation recovery time 55 ? ? ns v cc v cc output r2 50 pf including jig and scope gnd 90% 10% 90% 10% rise time = 1 v/ns fall time = 1 v/ns output v equivalent to: equivalent all input pulses r th r1 thevenin t cdr v dr > 1.5v data retention mode t r ce or v cc bhe . ble v cc(min.) v cc(min.) t cdr v dr > 1.5v data retention mode t r ce or v cc bhe . ble v cc(min.) v cc(min.) notes 8. tested initially and after any design or proce ss changes that may affect these parameters. 9. typical values are included for reference only and are no t guaranteed or tested. typical values are measured at v cc = v cc(typ) , t a = 25 c. 10. full device operation requires linear v cc ramp from v dr to v cc(min) > 200 s. 11. bhe .ble is the and of both bhe and ble . chip can be deselected by either disabling the chip enable signals or by disabling both byte enable pins.
cy62127dv30 document number: 38-05229 rev. *m page 6 of 14 switching characteristics (over the operating range) parameter [12] description cy62127dv30-55 unit min max read cycle t rc read cycle time 55 ? ns t aa address to data valid ? 55 ns t oha data hold from address change 10 ? ns t ace ce low to data valid ? 55 ns t doe oe low to data valid ? 25 ns t lzoe oe low to low z [13] 5 ? ns t hzoe oe high to high z [13, 14] ? 20 ns t lzce ce low to low z [13] 10 ? ns t hzce ce high to high z [13, 14] ? 20 ns t pu ce low to power-up 0 ? ns t pd ce high to power-down ? 55 ns t dbe ble /bhe low to data valid ? 55 ns t lzbe [15] ble /bhe low to low z [13] 5 ? ns t hzbe ble /bhe high to high z [13, 14] ? 20 ns write cycle [16] t wc write cycle time 55 ? ns t sce ce low to write end 40 ? ns t aw address setup to write end 40 ? ns t ha address hold from write end 0 ? ns t sa address setup to write start 0 ? ns t pwe we pulse width 40 ? ns t bw ble /bhe low to write end 40 ? ns t sd data setup to write end 25 ? ns t hd data hold from write end 0 ? ns t hzwe we low to high z [13, 14] ? 20 ns t lzwe we high to low z [13] 10 ? ns notes 12. test conditions assume signal transition time of 1v/ns or less, timing reference levels of v cc(typ.) /2, input pulse levels of 0 to v cc(typ.) , and output loading of the specified i ol . 13. at any temperature and voltage condition, t hzce is less than t lzce , t hzbe is less than t lzbe , t hzoe is less than t lzoe , and t hzwe is less than t lzwe for any device. 14. t hzoe , t hzce , t hzbe , and t hzwe transitions are measured when the outputs enter a high-impedance state. 15. if both byte enables are toggled together, this value is 10 ns. 16. the internal write time of the memory is defined by the overlap of we , ce = v il , bhe and/or ble = v il . all signals must be active to initiate a write and any of these signals can terminate a write by going inactive. the data input setup and hold timing should be referenced to the edge of the signal that terminates the write.
cy62127dv30 document number: 38-05229 rev. *m page 7 of 14 switching waveforms figure 1. read cycle no. 1 (a ddress transition controlled) [17, 18] figure 2. read cycle no. 2 (oe controlled) [17, 18, 19] figure 3. write cycle no. 1 (we controlled) [20, 21, 22, 23, 24] notes 17. device is continuously selected. oe , ce = v il , bhe , ble = v il . 18. we is high for read cycle. 19. address valid prior to or coincident with ce , bhe , ble transition low. 20. t hzoe , t hzce , t hzbe , and t hzwe transitions are measured when the outputs enter a high-impedance state. 21. the internal write time of the memo ry is defined by the overlap of we , ce = v il , bhe and/or ble = v il . all signals must be active to initiate a write and any of these signals can terminate a write by going inactive. the data input setup and hold timing should be referenced to the edge of the signal that terminates the write. 22. data i/o is high-impedance if oe = v ih . 23. if ce goes high simultaneously with we high, the output remains in a high-impedance state. 24. during the don't care period in the data i/o waveform, the i/os are in output state and input signals should not be applied. address data out previous data valid data valid t rc t aa t oha t hd t sd t pwe t sa t ha t aw t sce t wc t hzoe data in valid ce address we data i/o oe bhe /ble t bw don't care
cy62127dv30 document number: 38-05229 rev. *m page 8 of 14 figure 4. write cycle no. 2 (ce controlled) [25, 26, 27, 28, 29] figure 5. write cycle no. 3 (we controlled, oe low) [28, 29] switching waveforms (continued) t hd t sd t pwe t ha t aw t sce t wc t hzoe data in valid ce address we data i/o oe bhe / ble t bw t sa don't care data in valid t hd t sd t lzwe t pwe t sa t ha t aw t sce t wc t hzwe ce address we data i/o t bw bhe /ble don't care notes 25. t hzoe , t hzce , t hzbe , and t hzwe transitions are measured when the outputs enter a high-impedance state. 26. the internal write time of the memory is defined by the overlap of we , ce = v il , bhe and/or ble = v il . all signals must be active to initiate a write and any of these signals can terminate a write by going inactive. the data input setup and hold timing should be referenced to the edge of the signal that terminates the write. 27. data i/o is high-impedance if oe = v ih . 28. if ce goes high simultaneously with we high, the output remains in a high-impedance state. 29. during the don't care period in the data i/o waveform, the i/os are in output state and input signals should not be applied.
cy62127dv30 document number: 38-05229 rev. *m page 9 of 14 truth table figure 6. write cycle no. 4 (bhe -/ble -controlled, oe low) [30, 31] switching waveforms (continued) data i/o address t hd t sd t sa t ha t aw t wc ce we data in valid t bw bhe /ble t sce t pwe don't care notes 30. if ce goes high simultaneously with we high, the output remains in a high-impedance state. 31. during the don't care period in the data i/o waveform, the i/os are in output state and input signals should not be applied. ce we oe bhe ble i/o 0 ?i/o 7 i/o 8 ?i/o 15 mode power h x x x x high z deselect/power-down standby (i sb ) x x x h h high z deselect/power-down standby (i sb ) l h l l l read all bits active (i cc ) l h l h l read lower byte only active (i cc ) l h l l h read upper byte only active (i cc ) l h h l l output disabled active (i cc ) l h h h l output disabled active (i cc ) l h h l h output disabled active (i cc ) high z high z high z data out data out high z high z data out high z high z high z data out high z high z l l x l l data in data in write active (i cc ) l l l l x x h l l h data in high z high z data in write lower byte only write upper byte only active (i cc ) active (i cc )
cy62127dv30 document number: 38-05229 rev. *m page 10 of 14 ordering information cypress offers other versions of this type of product in many different configurations and features. the below table contains o nly the list of parts that are currently available. for a comp lete listing of all options, visit the cypress website at www.cypress.com and see product summary page at http://www.cypress.com/products or contact your local sales representative. cypress maintains a worldwide network of offices, solution center s, manufacturer's representatives and distributors. to find th e office closest to you, visit us at http://www.cypress.com/ go/datasheet/offices . ordering code definitions speed (ns) ordering code package diagram package type operating range 55 cy62127dv30ll-55bvxi 51-85150 48-ball fine pitch bga (6 mm 8 mm 1 mm) (pb-free) industrial temperature grade: i = industrial package type: (bvx = 48-ball fbga (pb-free); zx = 48-pin tsop i (pb-free)) 55 = speed grade ll = low power voltage range = 3 v typical d = process technology 130 nm bus width = 16 density = 1-mbit family code: mobl sram family company id: cy = cypress 621 cy 2 7 - ll xxx d 55 i v30
cy62127dv30 document number: 38-05229 rev. *m page 11 of 14 package diagrams 51-85150 *h 51-85087 *e
cy62127dv30 document number: 38-05229 rev. *m page 12 of 14 acronyms document conventions units of measure acronym description bhe byte high enable ble byte low enable cmos complementary metal oxide semiconductor ce chip enable i/o input/output oe output enable sram static random access memory tsop thin small outline package fbga fine-pitch ball grid array we write enable symbol unit of measure ns nanosecond vvolt a microampere ma milliampere pf picofarad c degree celsius wwatt
cy62127dv30 document number: 38-05229 rev. *m page 13 of 14 document history page document title: cy62127dv30 mobl ? 1-mbit (64 k 16) static ram document number: 38-05229 revision ecn orig. of change submission date description of change ** 117690 jui 08/27/02 new datasheet *a 127311 mpr 06/13/03 changed from advanced status to preliminary changed isb2 to 5 ? a (l), 4 ? a (ll) changed iccdr to 4 ? a (l), 3 ? a (ll) changed cin from 6 pf to 8 pf *b 128341 jui 07/22/03 changed from preliminary to final add 70-ns speed, updated ordering information *c 129000 cdy 08/29/03 changed icc 1 mhz typ from 0.5 ma to 0.85 ma *d 316039 pci see ecn added 45-ns speed bin in ac, dc and ordering information tables added footnote # 8 on page #4 added lead-free package ordering information on page# 9 changed 44-lead tsop-ii package name from z44 to zs44 *e 346982 aju see ecn added 56-pin qfn package *f 369955 syt see ecn added temperature ranges in the features section on page # 1 added automotive specs for i ix ,i oz ,i sb1 and i sb2 in the product portfolio on page #2 and the dc electrical characteristics table on page# 4 added automotive spec for i ccdr in the data retention characteristics table on page# 5 added pb-free automotive parts for 55 ns speed bin *g 457685 nxr see ecn removed 56-pin qfn package from product offering updated ordering information table *h 470383 nxr see ecn changed pin #23 of tsop ii from nc to dnu and updated footnote #2 *i 2897885 rame/nikm 03/22/10 removed inactive parts from the ordering information table. updated package diagrams. *j 3010373 aju 08/20/2010 updated features updated product portfolio updated operating range updated dc electrical characteristics updated data retention characteristics updated switching characteristics updated ordering information added ordering code definitions minor edits and updated in new template *k 3329789 rame 07/27/11 r emoved references to an10 64 sram system guidelines. updated template according to current cy standards. *l 3393183 rame 10/03/11 post to web. *m 3861271 tava 01/08/2013 updated ordering information (updated part numbers). updated package diagrams : spec 51-85150 ? changed revision from *g to *h. spec 51-85087 ? changed revision from *d to *e.
document number: 38-05229 rev. *m revised january 8, 2013 page 14 of 14 all products and company names mentioned in this document may be the trademarks of their respective holders. cy62127dv30 ? cypress semiconductor corporation, 2006-2013. the information contained herein is subject to change without notice. cypress s emiconductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or other rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement wi th cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. any source code (software and/or firmware) is owned by cypress semiconductor corporation (cypress) and is protected by and subj ect to worldwide patent protection (united states and foreign), united states copyright laws and internatio nal treaty provisions. cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the cypress source code and derivative works for the sole purpose of creating custom software and or firmware in su pport of licensee product to be used only in conjunction with a cypress integrated circuit as specified in the applicable agreement. any reproduction, modification, translation, compilation, or repre sentation of this source code except as specified above is prohibited without the express written permission of cypress. disclaimer: cypress makes no warranty of any kind, express or implied, with regard to this material, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose. cypress reserves the right to make changes without further notice to t he materials described herein. cypress does not assume any liability arising out of the application or use of any product or circuit described herein. cypress does not authori ze its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress? prod uct in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. use may be limited by and subject to the applicable cypress software license agreement. sales, solutions, and legal information worldwide sales and design support cypress maintains a worldwide network of offices, solution center s, manufacturer?s representatives, and distributors. to find t he office closest to you, visit us at cypress locations . products automotive cypress.co m/go/automotive clocks & buffers cypress.com/go/clocks interface cypress. com/go/interface lighting & power control cypress.com/go/powerpsoc cypress.com/go/plc memory cypress.com/go/memory optical & image sensing cypress.com/go/image psoc cypress.com/go/psoc touch sensing cyp ress.com/go/touch usb controllers cypress.com/go/usb wireless/rf cypress.com/go/wireless psoc solutions psoc.cypress.com/solutions psoc 1 | psoc 3 | psoc 5

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